1. Field of Invention
The present invention relates to a method of fabricating the thin film transistor array inside a liquid crystal display (LCD). More particularly, the present invention relates to a method of fabricating a thin film transistor array that minimizes damages due to electrostatic discharge (ESD).
2. Description of Related Art
Liquid crystal display (LCD) has many advantages over a cathode ray tube (CRT) such as a low operating voltage, radiation free, light and occupying a small volume. LCD together with other flat panel type display such as plasma displays and electroluminance displays has become one of the most researched types of displays. At present, active matrix liquid crystal display is often regarded as having the greatest potential to become a next generation product. However, as the number of scan lines is increased, duty cycles assigned by an external driver to each pixel will be reduced. Hence, there will be continuous deterioration of display properties in the display device.
An active array liquid crystal display has a transistor or a diode in each pixel electrode to serve as an active element controlling the writing of data into the liquid crystal display. Currently, thin film transistor liquid crystal display is regarded as the mainstream among other liquid crystal displays. When a pixel electrode is selected (that is, in an ‘on’ state), signal is written into the pixel. On the other hand, when the pixel electrode is de-selected (that is, in an ‘off’ state), a storage capacitor within each pixel unit maintains a potential in the liquid crystal layer within the display. Consequently, the liquid crystal and the duty cycle have a static property.
In general, the thin film transistor array within a thin film transistor display is fabricated using a ‘five photomask’ process as shown in FIGS. 1A to 1E. The photomask process includes operations such as photoresist coating, soft baking, hard baking, photo-exposure, photoresist fixing, chemical development and etching so that various thin films are patterned.
FIGS. 1A to 1E are schematic cross-sectional view showing the steps for fabricating conventional thin film transistor array. As shown in FIG. 1A, a first photomask is used to form a first metallic layer 102 over a substrate 100. The first metallic layer 102 is a patterned metallic layer comprising a gate 102a and a gate connected scan line 102b. 
As shown in FIG. 1B, a gate insulating layer 104 is formed over the gates 102a and the scan lines 102b over the substrate 100. Thereafter, a second photomask is used to form a channel layer 106 over the gate insulating layer 104 that crosses over the gate 102a. 
As shown in FIG. 1C, a third photomask is used to form a second metallic layer 110 over the substrate 100. The second metallic layer 110 mainly includes a source/drain 110a and a data line 110b with connection to one of the source/drain 110 terminals (the source terminal). In addition, the source/drain 110a are located on each side of the channel layer 106.
As shown in FIG. 1D, a passivation layer 112 is formed over the substrate 100 covering the thin films, that is, the first metallic layer 102, the gate insulating layer 104, the channel layer 106, the second metallic layer 110. A fourth photomask is used to form contact openings 114 in the passivation layer that expose the other terminal (the drain terminal) of the source/drain 110a. 
As shown in FIG. 1E, a fifth photomask is used to form a pixel electrode 116 over the passivation layer 112. The pixel electrode 116 may be fabricated using a material such as indium-tin oxide or indium-zinc oxide. Furthermore, the pixel electrode 116 is electrically connected to the other terminal (the drain terminal) of the source/drain 110a through the contact opening 114 in the passivation layer 112.
Aside from forming contact openings 114 in the fourth photomask step, openings 115a and 115b are also formed in the gate insulating layer 104 and the passivation layer 112 close to the edge of the substrate 100 as shown in FIG. 1F. FIG. 1F is a cross-section through a peripheral area of FIG. 1E. The openings 115a and 115b expose the first metallic layer 102 and the second metallic layer 110. The first metallic layer 102 and the second metallic layer 110 are electrically connected through the pixel electrode 116 only after the fifth photomask step is completed. In other words, before conductive the fourth photomask step, the first metallic layer 102 and the second metallic layer 110 are isolated from each other. Hence, the probability of having an electrostatic discharge (ESD) between the two metallic layers is rather high.
One method to reduce possible damages due to an ESD between the two metallic layers includes conducting one more photomask step to pattern the gate insulating layer. The patterned gate insulating layer has a short ring opening that exposes the first metallic layer electrically. The short ring opening permits an electrical connection of the subsequently formed second metallic layer with the underlying first metallic layer. However, this will increase the number of photomask step by one and hence add processing complexity as well as production cost.